1. Field of the Invention
The present invention refers to the leads of a No-Lead type package of a semi-conductor device, in particular but not exclusively to the leads of a Quad Flat No Lead type package of a semiconductor device.
2. Background of the Invention
Pursuing the evolution of integrated circuits, the manufacturing process of an integrated circuit has reached such levels of integration that there is the need to use package structures capable of meeting the increasingly insistent requests for reduction in cost, weight, section, and dimensions with the same reliability and usability.
These needs have been partially resolved through the introduction of a family of package commonly known as Chip Scale Package (CSP), whose characteristics include the reduction of dimension and weight, an easier assembly process, an increase in performance and a general reduction in production costs.
The reduction of dimensions and weight are probably the most important factors among these characteristics, for use of the CSP technology.
In particular CSP technology can be divided into two large package types: 1) the so-called Grid Arrays; 2) the so-called Quad Flat Leads.
A transversal section of a known package of the Quad Flat Leads (QFL) type is shown in FIG. 1.
The structure 1 of the QFL package, having a die pad 2 surrounded by a plurality of leads 3, can be seen in said FIG. 1. The presence of a chip 4 that has an active surface 5 and a rear surface 6 can also be noted. Chip 4 has its rear surface 6 connected to the die pad 1, while the active surface 5 provides for a plurality of bonding pads 7 for making the external connections of the chip 4 itself.
The bonding pads 7 are electrically connected to the leads 3 by means of bonding wires 8.
In addition a molding compound 9 normally encapsulates the whole chip 4, the die pad 1, the bonding wires 8 and a portion of the leads 3.
The QFL typology, just illustrated, in turn provides for a category without the leads themselves, that is the Quad Flat No-Lead o Leadless (QFN) typology.
A package like this carries to the extreme the concepts of miniaturization, as it presents a reduced package footprint, a thin profile and reduced weight.
Consequently, the manufacturers of video cameras, cellular telephones and laptops heavily rely on the use of QFN in their consumption products.
A section view of a Quad Flat No-Lead package of a semiconductor in accordance with the known art is shown in FIG. 2.
A plan view of the rear side corresponding to FIG. 2 is shown in FIG. 3.
As shown in FIGS. 2 and 3 this type of package 23 includes a die pad 10 that has a plurality 11 of leads surrounding the die pad 10 itself. The presence of a chip 12 that has an active surface 13 and a rear surface 14 can also be seen. On the active surface 13, there are a plurality of bonding pads 15 suited to enabling the external connection. The rear surface 14 of the chip 12 is connected to the upper surface 16 of the die pad 10 by means of an adhesive layer 17, while the bonding pads 15 are electrically connected to the upper surface 18 of the leads 11 respectively by means of a bonding wire 19.
In addition, the die pad 10 is usually connected to ground by means of a bonding wire 22 so as to increase the electrical performance through a reduction of the interferences.
A molding compound 60 encapsulates the whole chip 12, the bonding wires 19, and the upper surface 18 of the leads 11 while it exposes the lower surface 20 and the side surface 21 of the leads 11 for the external connections.
In fact the lower surface 20 of the leads 11 is successively welded to a PCB (Printed Circuit Board), as shown in FIG. 4, through technical means that are well known to a technician of the sector.
A micro-section 24 between a lead 11 and a bonding pad 25 of a PCB 26 is illustrated in said FIG. 4. There is a welding paste 27 between the lead 11 and the bonding pad 25 of the PCB 26.
The main problem of the QFN packages is caused by the non-alignment (mismatch) between the leads and the PCB, which is created during the turn on/turn off cycles of the device in the interval of the operative temperatures provided for, because of the different thermal expansion of the materials involved.
This brings high mechanical stress in the welding points between the leads and the PCB, as shown successively in FIG. 6.
This problem is accentuated because of the intrinsic structure of the QFN package, due that is to the shape of the contact pad and the dimensions of the pad, as the welding joint between the package QFN and the PCB is extremely small.
In fact, given the structure of the leads 11 of the QFN package, it is technically complex and economically unfavorable to increase the lower contact surface 20 of the leads 11 with the PCB, as this would lead to an increase in the footprint of the QFN package and therefore the occupation of a greater area.
The Applicant has carried out various turn on/off simulations of the chip 12, verifying the behavior of the welding points between QFN package and PCB, noting in particular that there are various problems, among which: 1) electrical failures; and 2) high torsion stress in the welding with consequent early mechanical breakages of the welding point.
A graph is represented in FIG. 5, having the number of cycles on the x coordinate and on the y coordinate the percentage of failures, of two devices, having different physical dimensions and represented respectively with a circle (device with greater dimensions) and a triangle (device with lower dimensions), from which it can be deducted that several cycles of turn off/on are enough (around a few hundred), in an interval of operative temperatures of between −40° C. and +150° C., to cause electrical failures of the welding joint.
In addition this phenomenon is overemphasized when the dimension of the package is increased.
The Applicant has also verified that breakages occur in the welding joints, when said devices are submitted to the same test cycles, that depend mainly on the dimension of the lead, noting that the smaller the lead is, sooner occur the breakages in contrast with what happens for electrical failures.
A micro-section 28 between a lead 11 and a pad 25 of a PCB is shown in FIG. 6. From this micro-section 28 a mismatch between lead 11 and pad 25 can be seen, with lack of welding material 27. This leads both to a deterioration of the electrical performance of the joint and to lower mechanical reliability of the joint.
Other problems that afflict the QFN packages can arise during the process of cutting the QFN package itself from the lead frame, a process known as a “singulation process”.
In fact, during this operation, as the leads 11 of the QFN package are cut mechanically by means of cutting tools and as these leads 11 are emerged in the plastic package 60, there is a possibility that when the cut is made a delaminating is created on the side surfaces 21 of the leads 11.
This means that the bonding wires 19 welded on the upper surface 18 of said leads 11 can be stressed, making the joint mechanically weak.
Unfortunately the common QFN packages show considerable delaminations between the end of the leads and the welding compound, with the obvious repercussions on the level of reliability of the device.
This inconvenience cannot be attenuated, not even with the use of refined and very expensive molding compounds.
Another inconvenience is found in the fact that following the operation of cutting the QFN package from the lead frame, the side surface 21 of the lead 11 is exposed to the ambient atmosphere.
As the lead 11 is generally made with a material such as copper, this oxidizes rapidly causing a drop in the electrical performance.
Another inconvenience that affects the QFN packages occurs when the QFN package itself is welded onto PCB.
In fact, a lead 11 of the QFN package only offers the lower surface 20 to carry out the operation of welding to the PCB.
This entails a welding joint having a reduced contact surface, thus making it weaker and thus more easily subjected to mechanical breakages.
In addition the material making up the leads 11 cannot be welded to the PCB until after an electroplating operation.
From what has been shown up to now, the doubtless advantages offered by the Quad Flat No Lead packages appear evident, but the number and type of technical problems that have to be dealt with in producing such packages are also evident.